asmext.inc

Author: Jonathan Weaver, jonw0224@netscape.net
Date: 11/1/2005
Version: 1.0
Filename: asmext.inc
Description: Extention of assembly instructions on registers and literals.

Procedure Heading List

ADDFF macro regA, regB, dest

ADDFF_TW macro regA, regB

ADDLF macro lit, reg, dest

ADDLF_TW macro lit, reg

ADDWPC macro TableStart, TableEnd

ANDFF macro regA, regB, dest

ANDFF_TW macro regA, regB

ANDLF macro lit, reg, dest

ANDLF_TW macro lit, reg

IORFF macro regA, regB, dest

IORFF_TW macro regA, regB

IORLF macro lit, reg, dest

IORLF_TW macro lit, reg

MOVFF macro regA, regB

MOVFF_TW macro regA, regB

MOVLF macro lit, reg

MOVLF_TW macro lit, reg

NEGATEF macro reg, dest

ROTL macro reg, lit

ROTR macro reg, lit

SHIFTL macro reg, lit

SHIFTR macro reg, lit

SUBFF macro regA, regB, dest

SUBFF_TW macro regA, regB

SUBLF macro lit, reg, dest

SUBLF_TW macro lit, reg

SWAPFF macro regA, regB

SWAPFF_TW macro regA, regB

SWAPWF macro reg

VROTL macro regA, regB

VROTR macro regA, regB

VSHIFTL macro regA, regB

VSHIFTR macro regA, regB

XORFF macro regA, regB, dest

XORFF_TW macro regA, regB

XORLF macro lit, reg, dest

XORLF_TW macro lit, reg

Procedure Descriptions

ADDFF macro regA, regB, dest
Description:
Adds regA to regB and stores in WREG or regB. Affects WREG, STATUS. 2 Instruction Cycles.
Parameters:
regA	the register to add to regB
regB	the register to add to regA
dest	literal equal to F to store in regB, W to store in WREG

ADDFF_TW macro regA, regB
Description:
Adds regA to regB and stores in regB, but preserves WREG. Affects STATUS. 5 Instruction Cycles.
Parameters:
regA	register to add to regB
regB	register to add to regA

ADDLF macro lit, reg, dest
Description:
Adds lit and reg and stores in WREG or reg. Affects STATUS, WREG. 2 Instruction Cycles.
Parameters:
lit	the literal to add with reg
reg	the register to add with lit
dest	literal equal to F to store in reg, W to store in WREG

ADDLF_TW macro lit, reg
Description:
Adds lit and reg and stores in reg, but preserves WREG. Affects STATUS. 4 Instruction Cycles.
Parameters:
lit	literal to add to reg
reg	register which to add literal

ADDWPC macro TableStart, TableEnd
Description:
Adds WREG to the Program Counter. Usually used to lookup a value in a table of retlw between labels TableStart and TableEnd. 1 to 6 Instruction Cycles.
Parameters:
TableStart	starting address in program memory of the table, should be immediately following call to ADDWPC
TableEnd	ending address in program memory of the table. For support if table crosses a page boundary (gives warning).

ANDFF macro regA, regB, dest
Description:
Ands regA and regB and stores in WREG or regB. Affects WREG, STATUS. 2 Instruction Cycles.
Parameters:
regA	the register to and with regB
regB	the register to and with regA
dest	literal equal to F to store in regB, W to store in WREG

ANDFF_TW macro regA, regB
Description:
Ands regA and regB and stores in regB, but preserves WREG. Affects STATUS. 5 Instruction Cycles.
Parameters:
regA	register to and with regB
regB	register to and with regA

ANDLF macro lit, reg, dest
Description:
Ands lit and reg and stores in WREG or reg. Affects WREG, STATUS. 2 Instruction Cycles.
Parameters:
lit	literal to and with reg
reg	register to and with lit
dest	literal equal to F to store in reg, W to store in WREG

ANDLF_TW macro lit, reg
Description:
Ands lit and reg and stores in reg, but preserves WREG. Affect STATUS. 7 Instruction Cycles.
Parameters:
lit	literal to and with reg
reg	register which to and with literal

IORFF macro regA, regB, dest
Description:
Inclusive ors regA and regB and stores in WREG or regB. Affects WREG, STATUS. 2 Instruction Cycles.
Parameters:
regA	the register to or with regB
regB	the register to or with regA
dest	literal equal to F to store in regB, W to store in WREG

IORFF_TW macro regA, regB
Description:
Inclusive ors regA and regB and stores in regB, but preserves WREG. Affects STATUS. 5 Instruction Cycles.
Parameters:
regA	register to inclusive or with regB
regB	register to inclusive or with regA

IORLF macro lit, reg, dest
Description:
Inclusive ors lit and reg and stores in WREG or reg. Affects WREG, STATUS. 2 Instruction Cycles.
Parameters:
lit	literal to inclusive or with reg
reg	register to inclusive or with lit
dest	literal equal to F to store in reg, W to store in WREG

IORLF_TW macro lit, reg
Description:
Inclusive ors lit and reg and stores in reg, but preserves WREG. Affects STATUS. 7 Instruction Cycles.
Parameters:
lit	literal to inclusive or with reg
reg	register which to inclusive or with literal

MOVFF macro regA, regB
Description:
Moves the value in regA to regB. Affects WREG, STATUS. 2 Instruction Cycles.
Parameters:
regA	the register to move to regB
regB	the destination register

MOVFF_TW macro regA, regB
Description:
Moves the value in regA to regB, but preserves WREG. Affects STATUS. 4 Instruction Cycles.
Parameters:
regA	register to move to regB
regB	destination register

MOVLF macro lit, reg
Description:
Moves lit to reg. Affects WREG. 2 Instruction Cycles.
Parameters:
lit	literal to move
reg	register to move literal to

MOVLF_TW macro lit, reg
Description:
Moves lit to reg, but preserves WREG. Affects STATUS. 4 instruction cycles.
Parameters:
lit	literal to move
reg	register to move literal to

NEGATEF macro reg, dest
Description:
Negates reg and stores in WREG or reg. Affects STATUS. 2 Instruction Cycles.
Parameters:
reg	register to negate (result is 0 - register)
dest	literal equal to F to store in reg, W to store in WREG

ROTL macro reg, lit
Description:
Rotates the value in reg left by lit and stores in reg. Affects WREG, STATUS. 1 to 4 Instruction Cycles.
Parameters:
reg	the register to shift
lit	a literal containing the number of bits to shift left

ROTR macro reg, lit
Description:
Rotates the value in reg left by lit and stores in reg. Affects WREG, STATUS. 1 to 4 Instruction Cycles.
Parameters:
reg	the register to shift
lit	a literal containing the number of bits to shift left

SHIFTL macro reg, lit
Description:
Shifts the value in reg left by lit and stores in reg. Affects WREG, STATUS. 2 to 5 Instruction Cycles.
Parameters:
reg	the register to shift
lit	a literal containing the number of bits to shift left

SHIFTR macro reg, lit
Description:
Shifts the value in reg right by lit and stores in reg. Affects WREG, STATUS. 2 to 5 Instruction Cycles.
Parameters:
reg	the register to shift
lit	a literal containing the number of bits to shift left

SUBFF macro regA, regB, dest
Description:
Subracts regA from regB and stores in WREG or regB. Affects STATUS, WREG. 2 Instruction Cycles.
Parameters:
regA	the register to subtract
regB	the register to subtract from
dest	literal equal to F to store in regB, W to store in WREG

SUBFF_TW macro regA, regB
Description:
Subracts regA from regB and stores in regB, but preserves WREG. Affects STATUS. 5 Instruction Cycles.
Parameters:
regA	register to subtract from regB
regB	register regA is subtracted from and the destination register

SUBLF macro lit, reg, dest
Description:
Subtracts reg from lit and stores in WREG or reg. Affects WREG, STATUS. 2 to 3 Instruction Cycles.
Parameters:
lit	literal to subtract from
reg	register to subtract from literal
dest	literal equal to F to store in reg, W to store in WREG

SUBLF_TW macro lit, reg
Description:
Subtracts reg from lit and stores in reg, but preserves WREG. Affects STATUS. 6 Instruction Cycles.
Parameters:
lit	literal to subtract reg from
reg	register to subtract from lit and destination register

SWAPFF macro regA, regB
Description:
Sets regA equal to regB and regB equal to regA. Affects STATUS, WREG. 4 Instruction Cycles.
Parameters:
regA	register to move to regB
regB	register to move to regA

SWAPFF_TW macro regA, regB
Description:
Sets regA equal to regB and regB equal to regA, but preserves WREG. Affects STATUS. 8 Instruction Cycles.
Parameters:
regA	register to move regB to
regB	register to more regA to

SWAPWF macro reg
Description:
Sets WREG equal to reg and reg equal to WREG. Affects STATUS. 2 Instruction Cycles.
Parameters:
reg	the register to swap with WREG

VROTL macro regA, regB
Description:
Rotates regA left by regB. Requires 11 program words and 11 cycles. Affects WREG and STATUS.
Parameters:
regA	register to rotate
regB	register that determines rotate (7 to 0 are valid)

VROTR macro regA, regB
Description:
Rotates regA right by regB. Requires 11 program words and 11 cycles. Affects WREG and STATUS.
Parameters:
regA	register to rotate
regB	register that determines rotate (7 to 0 are valid)

VSHIFTL macro regA, regB
Description:
Shifts regA left by regB. Requires 13 program words and 13 cycles. Affects WREG and STATUS.
Parameters:
regA	register to shift
regB	register that determines shift (7 to 0 are valid)

VSHIFTR macro regA, regB
Description:
Shifts regA right by regB. Requires 13 program words and 13 cycles. Affects WREG and STATUS.
Parameters:
regA	register to shift
regB	register that determines shift (7 to 0 are valid)

XORFF macro regA, regB, dest
Description:
Exclusive ors regA and regB and stores in WREG or regB. Affects STATUS, WREG. 2 Instruction Cycles.
Parameters:
regA	the register to exclusive or with regB
regB	the register to exclusive or with regA
dest	literal equal to F to store in regB, W to store in WREG

XORFF_TW macro regA, regB
Description:
Exclusive ors regA and regB and stores in regB, but preserves WREG. Affects STATUS. 5 Instruction Cycles.
Parameters:
regA	register to exclusive or with regB
regB	register to exclusive or with regA

XORLF macro lit, reg, dest
Description:
Exclusive ors lit and reg and stores in WREG or reg. Affects WREG, STATUS. 2 Instruction Cycles.
Parameters:
lit	literal to exclusive or with reg
reg	register to exclusive or with literal
dest	literal equal to F to store in reg, W to store in WREG

XORLF_TW macro lit, reg
Description:
Exclusive ors lit and reg and stores in reg, but preserves WREG. Affects STATUS. 4 Instruction Cycles.
Parameters:
lit	literal to exclusive or reg with
reg	register to exclusive or with lit and destination register